This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-324201, filed Nov. 15, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a synchronous signal generation circuit, particularly, to a synchronous signal generation circuit generating an internal clock signal in synchronism with an external clock signal supplied at a predetermined period, said internal clock signal being used for a high speed data transfer.
A In a conventional synchronous signal generation circuit, an internal clock signal is generated in synchronism with an external clock signal supplied to a memory device for use in a high speed data transfer. Since delay occurs in a circuit such as, for example, an input receiver in the input stage and in a circuit such as, for example, an off-chip driver in the output stage, the delay is corrected by using a synchronous circuit within the memory device.
FIG. 1 shows the construction of a conventional synchronous signal generation circuit including a mirror-type synchronous circuit as a main portion.
The synchronous signal generation circuit shown in FIG. 1 comprises a real circuit including an input receiver 1, a mirror-type synchronous circuit 2 and an off-chip driver 3 and a dummy circuit 6a surrounded by a dotted line and including an input receiver 4 and an off-chip driver 5.
A small amplitude external clock signal n0a supplied to the memory is inputted to the input receiver 1 of the real circuit, and a large amplitude signal n1a of CMOS level is outputted from the input receiver 1. In this case, a delay time D1r occurs within the input receiver 1.
The large amplitude signal n1a of CMOS level is branched so as to be supplied both to the input receiver 4 of the dummy circuit 6a and to the mirror-type synchronous circuit 2 of the real circuit. In the path of the real circuit, the signal n1a is transmitted through the mirror-type synchronous circuit 2 so as to be outputted from the mirror-type synchronous circuit 2 as a large amplitude signal n4a of CMOS level. The signal n4a is supplied to the off-chip driver 3 and is outputted from the off-chip driver 3 as a small amplitude internal clock signal n5a. A delay time Dr2 occurs within the off-chip driver 3.
In the path of the dummy circuit 6a surrounded by the dotted line, the signal n1a is supplied to the input receiver 4 of the dummy circuit 6a, and a large amplitude signal n2a of CMOS level is outputted from the input receiver 4. The signal n2a is supplied to the off-chip driver 5, and a large amplitude signal n3a of CMOS level is outputted from the off-chip driver 5 for driving the mirror-type synchronous circuit 2. In this step, a delay time D1d and another delay time D2d occur in the input receiver 4 and the off-chip driver 5, respectively.
In order to enable the synchronous signal generation circuit, which receives the external clock signal n0a, to output the internal clock signal n5a in synchronism with the external clock signal n0a, it is necessary for the sum of the delay time of the external clock signal n0a and the delay time of the internal clock signal n5a to be exactly equal to an integral multiple of the period T of the external clock signal n0a. An example, in which the sum of the delay time of the external clock signal n0a and the delay time of the internal clock signal n5a is equal to a single period, will now be described.
The input signal n1a to the input receiver 4 is transmitted through the mirror-type synchronous circuit 2 via the path of the dummy circuit 6a. In this step, the input signal n1a is triggered directly by the pulse rising edge of the pulse of the mirror-type synchronous circuit 2, with the result that the delay time in the mirror-type synchronous circuit 2 is Txe2x88x92(D1d+D2d).
Incidentally, it should be noted that the mirror-type synchronous circuit 2 is constructed such that the upper and lower portions have the same structure. Therefore, if the mirror-type synchronous circuit 2 is constructed such that a delay time of Txe2x88x92(D1d+D2d) occurs when the signal passing through the dummy circuit 6a is transmitted through the upper portion of the mirror-type synchronous circuit 2 as denoted by a broken line, a delay time when the signal passing through the real circuit joined by a solid line is transmitted through the lower portion of the mirror-type synchronous circuit 2 as denoted by an arrow of a solid line is equal to Txe2x88x92(D1d+D2d). It follows that the sum of the delay time in the path of the real circuit is D1r+Txe2x88x92(D1d+D2d)+D2r. To make the sum of the delay time noted above equal to the period T and to obtain the internal clock signal n5a in synchronism with the external clock signal n0a, it is necessary for the delay times to meet the relationship D1r+D2r=D1d+D2d. In short, the delay time of the signal transmitted through the path of the dummy circuit must be equal to the delay time of the signal transmitted through the path of the real circuit excluding the mirror-type synchronous circuit. In other words, in order to allow the internal clock signal n5a outputted from the synchronous signal generation circuit to be synchronized with the external clock signal n0a, it is necessary for the delay time in the dummy circuit to imitate completely the delay time in the real circuit. Further, in terms of the manufacturing process, it is desirable for the relationships D1r=D1d and D2r=D2d to be satisfied.
FIG. 2 is a timing wave form diagram denoting the operation of the conventional synchronous signal generation circuit. The signal n0a is a small amplitude external clock signal supplied to the input receiver 1. The period T of the wave form of the signal n0a is denoted by an arrow. The signal n1a represents the output signal generated from the input receiver 1. As shown in the drawing, the signal n1a is inputted to the input receiver 4 of the dummy circuit 6a with a delay time D1r and is outputted from the input receiver 4 as the large amplitude signal n2a of CMOS level with a delay time D1d. Further, the signal n2a is inputted to the off-chip driver 5 of the dummy circuit 6a and is outputted from the off-chip driver 5 as a large amplitude signal n3a of CMOS level with a delay time D2d. 
The signal n3a is inputted to the mirror-type synchronous circuit 2. However, since the delay time of the signal n3a is set at Txe2x88x92(D1d+D2d), the dummy output signal (not shown) transmitted through the mirror-type synchronous circuit 2 via the dummy circuit 6a is a signal delayed from the signal n1a by a period T.
On the other hand, in the real circuit, the large amplitude output signal n1a of CMOS level generated from the input receiver 1 is inputted to the mirror-type synchronous circuit 2 in which the delay time is set at Txe2x88x92(D1d +D2d), and the output signal n4a generated from the mirror-type synchronous circuit 2 is inputted to the off-chip driver 3 and, then, outputted from the off-chip driver 3 as a small amplitude internal clock signal n5a with a delay time D2r. 
In the timing wave form shown in FIG. 2, the delay times Txe2x88x92(D1d+D2d) of the mirror-type synchronous circuit after transmission of the signal through the dummy circuit 6a and during transmission of the signal through the real circuit are denoted respectively as MIRROR by arrows. It should be noted that the small amplitude internal clock signal n5a synchronized with the small amplitude external clock signal n0a is outputted from the off-chip driver 3 with the delay time D2r from the rising edge of the signal n4a. Incidentally, the timing wave form shown in FIG. 2 covers the case where D1r+D2r is equal to D1d+D2d. 
As described above, in the dummy circuit 6a of the conventional synchronous signal generation circuit, the input signal is supplied first to the input receiver 4 and, then, to the off-chip driver 5. Also, the input receiver 1 of the real circuit converts the small amplitude external clock signal n0a into the large amplitude signal n1a of CMOS level, and the off-chip driver 3 of the real circuit converts the large amplitude signal n4a of CMOS level into the small amplitude internal clock signal n5a. 
As described above, the signals inputted to and outputted from the mirror-type synchronous circuit 2 are large amplitude signals of CMOS level in the conventional synchronous signal generation circuit, giving rise to the problem that it is unavoidable for all the signals inputted to and outputted from the input receiver 4 and the off-chip driver 5 collectively constituting the dummy circuit 6a to be large amplitude signals of CMOS level.
As described above, the input receiver 1 and the off-chip driver 3 included in the real circuit differ from the input receiver 4 and the off-chip driver 5 collectively constituting the dummy circuit 6a in the input and output signal levels, making it impossible to form the real circuit and the dummy circuit by using the same circuits including the input and output signal levels in the conventional synchronous signal generation circuit.
Further, if the process dispersion, the power source variation, etc. are taken into account, a deviation in delay time occurs between the real circuit and the dummy circuit 6a. The deviation noted above brings about an error in synchronization between the external input clock signal and the internal clock signal outputted from the synchronous signal generation circuit.
As pointed out above, the conventional synchronous signal generation circuit was defective in that it was impossible to form the real circuit excluding the mirror-type synchronous circuit and the dummy circuit imitating the real circuit by using the same input receiver and the off-chip driver.
The present invention, which has been achieved for overcoming the above-noted problems, is intended to provide a synchronous signal generation circuit, in which the real circuit and the dummy circuit are disposed to be capable of forming the real circuit and the dummy circuit by using exactly the same input receiver and the off-chip driver including the input and output signal levels so as to suppress the occurrence of an error in the synchronization caused by the process dispersion or the power source variation.
In the synchronous signal generation circuit of the present invention, the dummy circuit used for setting up the delay time of the mirror-type synchronous circuit is constructed such that the input order of the signal to the input receiver and to the off-chip driver is opposite to that in the conventional synchronous signal generation circuit. To be more specific, in the dummy circuit of the synchronous signal generation circuit, the off-chip driver is arranged in the front stage and the input receiver is arranged in the rear stage. In other words, the input portion of the input receiver included in the dummy circuit is connected to the output portion of the off-chip driver included in the dummy circuit.
If the dummy circuit is constructed in the particular fashion, the off-chip driver of the dummy circuit receives a large amplitude signal outputted from the input receiver of the real circuit so as to output a small amplitude signal. On the other hand, the input receiver of the dummy circuit receives the small amplitude signal outputted from the off-chip driver of the dummy circuit so as to output a large amplitude signal. The large amplitude signal outputted from the input receiver of the dummy circuit is inputted to the mirror-type synchronous circuit of the real circuit.
To be more specific, if the arrangement of the off-chip driver and the input receiver collectively constituting the dummy circuit is made opposite to that in the conventional synchronous signal generation circuit, the input receiver and the off-chip driver included in the real circuit can be used as they are, with the result that the level alignment and the delay time alignment of the signals transmitted through the real circuit excluding the mirror-type synchronous circuit and the dummy circuit can be achieved simultaneously.
According to a first aspect of the present invention, there is provided a synchronous signal generation circuit for generating an internal clock signal in synchronism with an external clock signal having a predetermined period, comprising:
a real circuit including a first input receiver for receiving the external clock, a mirror-type synchronous circuit, and a first off-chip driver for outputting the internal clock signal, which are connected in series; and
a dummy circuit for determining a delay time in the mirror-type synchronous circuit, the dummy circuit including a second input receiver and a second off-chip driver coupled between the first input receiver and the mirror-type synchronous circuit;
wherein an input portion of the second input receiver is connected to an output portion of the second off-chip driver in the dummy circuit.
In the synchronous signal generation circuit of the present invention, it is desirable for the signal levels of the input signals to the first and second input receivers to be equal to each other, for the signal levels of the output signals of the first and second input receivers to be equal to each other, for the signal levels of the input signals to the first and second off-chip drivers to be equal to each other, and for the output signals from the first and second off-chip drivers to be equal to each other.
Also, in the synchronous signal generation circuit of the present invention, it is desirable for the signal levels of the input signals to the first and second input receivers to be smaller than the signal levels of the output signals from the first and second input receivers.
Also, in the synchronous signal generation circuit of the present invention, it is desirable for the signal levels of the input signals to the first and second off-chip drivers to be larger than the signal levels of the output signals from the first and second off-chip drivers.
Also, in the synchronous signal generation circuit of the present invention, it is desirable for the signal levels of the input signals to the first and second input receivers to be smaller than the signal levels of the output signals from the first and second input receivers, for the signal levels of the input signals to the first and second off-chip drivers to be larger than the signal levels of the output signals from the first and second off-chip drivers.
Also, in the synchronous signal generation circuit of the present invention, it is desirable for the first and second input receivers to be equal to each other in the method of connecting the circuit elements and for the first and second off-chip drivers to be equal to each other in the method of connecting the circuit elements.
Also, in the synchronous signal generation circuit of the present invention, it is desirable for the gradient of the output signal rise of the second input receiver to be set optionally.
Also, in the synchronous signal generation circuit of the present invention, it is desirable for the gradient of the output signal rise of the second off-chip driver to be set optionally.
Also, in the synchronous signal generation circuit of the present invention, it is desirable for the gradient of the output signal rise of the second input receiver to be set optionally, and for the gradient of the output signal rise of the second off-chip driver to be set optionally.
Also, in the synchronous signal generation circuit of the present invention, it is desirable for the first off-chip driver in the real circuit to comprise a circuit including at least a p-channel transistor having a gate width Wpr, an n-channel transistor having a gate width Wnr, a resistor having a resistance Rr, and a capacitor having a capacitance Cr, and for the second off-chip driver in the dummy circuit to comprise a circuit including a p-channel transistor having a gate width Wpd, an n-channel transistor having a gate width Wnd, a resistor having a resistance Rd, and a capacitor having a capacitance Cd, wherein the circuits are constructed to meet relationships Wpd=Wpr/a, Wnd=Wnr/a, Rd=Rrxc3x97a, and Cd=Cr/a, where the scaling ratio xe2x80x9caxe2x80x9d is larger than 1, i.e., a greater than 1.
Also, in the synchronous signal generation circuit of the present invention, it is desirable for each of the first and second off-chip drivers to comprise a p-channel transistor, an n-channel transistor, a first resistor, a second resistor, and a capacitor,
wherein a first power source voltage is imparted to the source of the p-channel transistor, the drain of the p-channel transistor is connected to the drain of the n-channel transistor, a second power source voltage is imparted to the source of the n-channel transistor, the drains of the p-channel transistor and the n-channel transistor, which are connected to each other, are connected to one terminal of the first resistor, the other terminal of the first resistor is connected to one terminal of the second resistor, a voltage that is a half of the first power source voltage is imparted to the other terminal of the second resistor, the connection point between the other terminal of the first resistor and one terminal of the second resistor is connected to one terminal of the capacitor, and a second power source voltage is imparted to the other terminal of the capacitor,
each of the first and second off-chip drivers comprises an input section comprising the gate of the p-channel transistor and the gate of the n-channel transistor and an output section including the connection point of the other terminal of the first resistor, one terminal of the second resistor, and one terminal of the capacitor, and
each of the first and second off-chip drivers is constructed to meet relationships Wpd=Wpr/a, Wnd=Wnr/a, Rd=Rrxc3x97a, and Cd=Cr/a, where wpr represents the gate width of the p-channel transistor included in the first off-chip driver, Wnr represents the gate width of the n-channel transistor included in the first off-chip driver, Rr represents the resistance of each of the first and second resistors included in the first off-chip driver, Cr represents the capacitance of the capacitor included in the first off-chip driver, wpd represents the gate width of the p-channel transistor included in the second off-chip driver, Wnd represents the gate width of the n-channel transistor included in the second off-chip driver, Rd represents the resistance of each of the first and second resistors included in the second off-chip driver, Cd represents the capacitance of the capacitor included in the second off-chip driver, and the scaling ratio xe2x80x9caxe2x80x9d is larger than 1, i.e., a greater than 1.
Further, in the synchronous signal generation circuit of the present invention, it is desirable for each of the first and second off-chip drivers to comprise a p-channel transistor, an n-channel transistor, a resistor and a capacitor,
wherein a first power source voltage is imparted to the source of the p-channel transistor, the drain of the p-channel transistor is connected to the drain of the n-channel transistor, a second power source voltage is imparted to the source of the n-channel transistor, the drains of the p-channel transistor and the n-channel transistor, which are connected to each other, are connected to one terminal of the resistor, the other terminal of the resistor is connected to one terminal of the capacitor, and the second power source voltage is imparted to the other terminal of the capacitor,
each of the first and second off-chip drivers comprises an input section including the gate of the p-channel transistor and the gate of the n-channel transistor, and an output section including the connection point of the other terminal of the resistor and one terminal of the capacitor, and
each of the first and second off-chip drivers is constructed to meet relationships Wpd=Wpr/a, Wnd=Wnr/a, Rd=Rrxc3x97a, and Cd=Cr/a, where Wpr represents the gate width of the p-channel transistor included in the first off-chip driver, Wnr represents the gate width of the n-channel transistor included in the first off-chip driver, Rr represents the resistance of the resistor included in the first off-chip driver, Cr represents the capacitance of the capacitor included in the first off-chip driver, Wpd represents the gate width of the p-channel transistor included in the second off-chip driver, Wnd represents the gate width of the n-channel transistor included in the second off-chip driver, Rd represents the resistance of resistor included in the second off-chip driver, Cd represents the capacitance of the capacitor included in the second off-chip driver, and the scaling ratio xe2x80x9caxe2x80x9d is larger than 1, i.e., a greater than 1.
In the synchronous signal generation circuit of the present invention constructed as pointed out above, the delay time in the dummy circuit relative to the real circuit excluding the mirror-type synchronous circuit is rendered equal regardless of generation of the process dispersion and the power source voltage variation so as to improve the synchronizing accuracy.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.